Level 1 and level 2 cache will remain implemented in SRAM, at least for now. And NAND flash memory will remain the king of the NVM hill for low-cost and high-density.

When the CPU runs an operation that wants to read or write data from/to the memory, it starts by checking the tags in the Level 1 cache. If the required one is present (a cache hit ), that data ...

Fig.8: L2 cache memory copy performance(1) Fig.9: L2 cache memory copy performance (2) 5. Conclusions The major impact of deploying an L2 cache in a high performance embedded device is the performance ...