This is how cache reading works. Intel Haswell diagram. Note how much real estate is used by the L3 cache and the Memory Controller. Early computers ran so slowly that cache really didn’t matter.

Grenoble, November 6th, 2009-- The Enabler of mixed signal Systems-on-Chip proposes a new breed of cache controller, dynamically self-configured to minimize power consumption. Traditional cache ...

To bring the performance of memory-intensive applications to the next level, the L2 cache controller of the A27L2 and AX27L2 further raise memory bandwidth by 2x and reduce memory latencies by 70%.