Cross-temperature testing for writing and reading across the data sheet temperature range can be considered when there are demonstrated sensitivities for programming at low and reading at high temperatures or visa-versa.

Data Retention is a measure of the ability of a memory cell in an NVM array to retain its charge state in the absence of applied external bias. Data retention failure occurs when a memory cell loses or gains charge to the extent that it is no longer detected to be in its intended data state.

This application note provides a perspective on nonvolatile flash memory reliability testing methodology and discusses the influence of key factors in terms of Program/Erase endurance and data retention.

Efficient programming of the MSP430 flash is governed by two major requirements: supply voltage (DVCC) and the flash timing generator clock (f FTG). For the MSP430F1xx and most of the MSP430F4xx family of devices, the supply voltage must be a minimum of 2.7 V.

PCHTDR checks the data retention of cycled devices at a high temperature. As shown by comparing Table 1 (page 2) and Table 2 (page 3), Micron's NOR Flash testing conditions meet JESD47I requirements without exception.

For retention testing, a temperature acceleration model is used where the memory is baked at temperatures as high as 125°C and the results are fit to confirm data retention time at system temperatures. Reliability testing procedures are done in such a way as to consider the real application usage and the technology failure modes.

The high temperature storage test is typically used to determine the effects of time and temperature, under storage conditions, for thermally activated failure mechanisms and time-to failure distributions of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms).

Endurance and retention qualification specifications (for cycle counts, durations, temperatures, and sample sizes) are specified in JESD47 or may be developed using knowledge-based methods as in JESD94.

The JEDEC JESD47 test spec for flash memory is a Stress-Test-Driven Qualification of Integrated Circuits that specifies qualification requirements (test times, temperatures, sample sizes, etc.) to reflect the dominant failure mechanisms under realistic use

JESD47I requires two different tests to validate data retention: • The uncycled high-temperature data retention (UCHTDR) test is performed on uncy-cled devices at 125°C. A data pattern is input, samples are submitted to high tempera-ture storage for 1000 hours.