\$\begingroup\$ You should edit the question to add a followup that shows the complete code for the second module that you're now using, along with the exact error message that the tool is giving you. \$\endgroup\$ –

Jul 4, 2015 · I am trying to call one of the 2 modules (fifo_test_1 or fifo_test_2) depending on the value of bit data[0] in the following Verilog code. input [10:0] data; always @ (data[0]) begin. if(~data[0]) begin. fifo_test_1 t1(.buf_in(data)); end. else if (data[0]) begin. fifo_test_2 t2 (.buf_in(data)); end.

Mar 5, 2008 · If you want to include a verilog code, then remove module and endmodule from comparator.v. That way your include will be plain Verilog code as part of test_module. It will work fine in synthesis and simulation.

Oct 15, 2013 · While inside a module A I'm trying to use the output of a module B as the input of another module C. Essentially this is a "go" switch that is flipped in module B after certain conditions are met and then this is supposed to be the trigger for module C to activate.

So that means we need a multiplexer. Well, we can either do this in continuous assignment using the ternary operator (?), or we can use an always block. Let's look at both. First the ternary: assign c = x ? xor21_output : and21_output; Then the always block (see note):

Sep 19, 2013 · Just instantiate them. add instantiated twice with block names of add_0add_1. for different modules just instantiate them as you would a your main block in a testharness.

Mar 4, 2024 · In Verilog, module instantiation refers to the process of using one module within another. When instantiating modules, you need to connect the inputs and outputs of the instantiated module (referred to as the submodule) to the ports of the parent module.

Nov 14, 2022 · If you were compile ALU1.sv into one library and ALU2.sv into another library, and both files included not_module.sv, then you wind up with two copies of the same module definition in two different libraries.

Sep 4, 2020 · From what little code you have shown, I don’t see why you don’t just find your module and interface directly into the dut. It would help if you could explain what “not working” means. Are you getting a compiler error, or getting results different from what you were expected?

Jul 11, 2015 · From your code it looks like you are trying to define a module (simple_function) inside of another module (function_calling), which is not allowed. Your function does not need to be contained inside a module. You should change myfunction.v to just contain the myfunction definition and remove the simple_function module entirely.