Our main goal in this paper is to develop an efficient architecture for the 2D convolution using control blocks. Hardware implementation of this 2D algorithm can be realized by a reduced number of shift registers, multipliers, adders, and control blocks, thus leading to considerable hardware saving and fewer number LUTs.

Abstract— Image processing is a growing field with tremendous potential and scope for development. With the advent of advanced visual technologies, there is a need to have an ultra high speed processing machines to match the quality of the

Energy efficient image convolution can be performed by re-ducing the energy consumption in the memory and the latency of the system by processing multiple pixels simultaneously. We propose the following optimizations for energy efficient image convolution: Memory Scheduling: Major source of energy con-sumption in on-chip designs is memory ...

Jul 29, 2024 · We’re exploring how to perform complex image convolutions using Field-Programmable Gate Arrays (FPGAs), a venture that combines the flexibility of software with the speed of hardware. Why FPGAs for convolution?

This is the code corresponding to the implementation of the hardware design described in this paper. It takes into account the reduced amount of memory available in the FPGA and makes an efficient use of those resources. It also achieves high throughout due to the pixel parallel processing. Simplified block diagram of the system.

Abstract—This paper presents a direct method of reducing convolution processing time using hardware computing and implementations of discrete linear convolution of two finite length sequences (NXN). This implementation method is realized …

Mar 12, 2019 · This thesis work emphasizes on the implementation of proposed computationally efficient convolution filter on a Xilinx Spartan3 FPGA platform.

The algorithms presented in this thesis were written for two FPGA architectures. The advantages of these devices have proven themselves for this type of design.

Jan 22, 2025 · Hardware implementation of image processing algorithms on FPGAs present notable advantages over software-based methods. Such implementations enable parallel processing and pipelining, thereby expediting image processing and analysis, particularly beneficial in real-time scenarios.

The implementation exploits the inherent parallelism of ConvNets and takes full advantage of multiple hardware multiplyaccumulate units on the FPGA and can be used for low-power, lightweight embedded vision systems for micro-UAVs and other small robots.