For those looking to dive into the deep end of SerDes development, take a look at this example on how to generate synthesizable RTL code for a dual-summing-node DFE using SerDes Toolbox, HDL Coder ...

In the diagram, a 2-bit magnitude comparator is split into two blocks: digital and analog. The digital portion of the circuit is implemented using Verilog. For the analog portion, the two 3-input ”OR” ...

RTL, Test Bench Code and output Graph for 'AND gate' in Structural ...