To test our code, we need a testbench which is just a way to say a piece of Verilog code that works like the outside world to our unit under test (in this case, the whole design).

That way regenerating the test bench won’t clobber your code. These are all simple changes, but they pay off. If you use no options, you get sensible defaults.

TestBencher Pro v8.0 adds support for mixed C++ and hardware description language (HDL) test benches using the open standard TestBuilder library. This library offers useful verificatio ...