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IEEE18y
Improved VHDL Input for High-Level Synthesis Tool xTractor
In this paper, an improved version of VHDL compiler for an academic high-level synthesis tool xTractor is presented. A synthesizable subset of behavioral VHDL, accepted by the compiler, is described ...
IEEE13y
Synthesis of VHDL code for FPGA design flow using Xilinx PlanAhead tool - IEEE Xplore
Abstract: This paper addresses a synthesis process of VHDL code for FPGA design flow using Xilinx PlanAhead tool. This tool provide a low power profile, more hard IP functionality, create a global ...