Assertion is a very powerful feature of System Verilog HVL (Hardware Verification Language). Nowadays it is widely adopted and used in most of the design verification projects. This article explains ...

For some piece of code which is common and frequently used in different and completely isolated modules, the function/task can’t be directly reused due to their access boundary limitations. To take a ...

The difference is simple ... design). The code will never synthesize, so we can use strange Verilog features that we don’t normally use in our regular code. The first thing to do is create a ...

The hardware engineer quickly wants to move on to more interesting examples that reflect the problems of hardware design. A simple example that tests ... program executes the generated file. In ...