As CMOS evolves from 32 nm down to 16 nm technologies, several technological changes suggest we can more efficiently use linear RC approximations to model the input stages of NMOS & PMOS. This ...

Abstract: In this letter, a novel dual high-/spl kappa/ approach, different high-/spl kappa/ dielectrics in nMOS and pMOS, with poly Si gate electrode is introduced. By turning the Fermi-pinning ...