The SSD SC730 is less than 4 cm short and can be connected to USB-A and USB-C via a slider. It is also sufficiently fast.

The new processors with stack cache are due to be launched on March 12, 2025. They will cost the same as their predecessors.

The eMMC 5.1 Memory controller is compliant with the latest eMMC 5.1 specification released by JEDEC. The controller provides a peak bandwidth of 104MB/s and supports all of the security features ...

The eMMC 5.0 / SD3.0 Host Controller IP (3MCR) is a highly integrated host controller IP solution that supports three key memory and I/O technologies: 1) SD, 2) SDIO and 3) eMMC memory formats. ...

Expansion of a planned spent nuclear fuel repository in Finland (no. 6) (March 2009) ...