In a hierarchical VLSI layout design, the block-level layout design is called a "chip floor plan." In this paper, a semi-automatic VLSI chip floor plan algorithm and its implementation are presented.

Implemented a department that assists in the presentation and management of hierarchical menus for applications Console (interface & Delegate). - ...

Implemented a department that assists in the presentation and management of hierarchical menus for applications Console (interface & Delegate). - ...