To design and implement half subtractor and full subtractor circuit and verify its truth table. Subtractor circuits take two binary numbers as input and subtract one binary number input from the other ...

AIM: To design a half subtractor and full subtractor circuit and verify its truth table in Quartus using Verilog programming.

A hybrid SET-CMOS based half subtractor is presented in this paper. Combination of CMOS and SET technology facilitates new advantageous functionalities. The proposed hybrid SET-CMOS based half ...

A hybrid SET-CMOS based half subtractor is presented in this paper. Combination of CMOS and SET technology facilitates new advantageous functionalities. The proposed hybrid SET-CMOS based half ...