News

GitHub8mon
kishore07062005/Implementation-of-half-subractor-and-full-subractor-circuit-using-Verilog-HDL - GitHub
Subtractor circuits take two binary numbers as input and subtract one binary number input from the other binary number input. Similar to adders, it gives out two outputs, difference and borrow ...
IEEE5y
Logic Encryption of Combinational Circuits - IEEE Xplore
Abstract: Logic encryption for combinational circuits are proposed in this paper. Logic encryption is achieved by using key gate transistors in the circuit schematic of subtractors and adders. In this ...
IEEE1y
Performance Evaluation of Novel Ternary Subtractor Circuits using Double Pass Transistor Logic - IEEE Xplore
Abstract: This paper proposes a novel circuit design of two Ternary Half Subtractor (THS) and a Ternary Full Subtractor (TFS) using Double pass transistor logic (DPL). The proposed THS is implemented ...
GitHub11mon
RahulM2005R/Implementation-of-half-subractor-and-full-subractor-circuit-using-Verilog-HDL - GitHub
Subtractor circuits take two binary numbers as input and subtract one binary number input from the other binary number input. Similar to adders, it gives out two outputs, difference and borrow ...