Date: 28.4.23 Implementation of half subtractor and full subtractor circuit using Verilog HDL Aim : To design and implement half subtractor and full subtractor circuit and verify its truth table.

To design a half adder and half subtractor circuit and verify its truth table in Quartus using Verilog programming.

A hybrid SET-CMOS based half subtractor is presented in this paper. Combination of CMOS and SET technology facilitates new advantageous functionalities. The proposed hybrid SET-CMOS based half ...

Logic encryption for combinational circuits are proposed in this paper. Logic encryption is achieved by using key gate transistors in the circuit schematic of subtractors and adders. In this work, two ...