The D input will be tied to a logic 1. Key Verilog Point #2: Blocking vs Non-Blocking Assignments Did you notice that some assignments use = and some use <=? This is an important Verilog feature.

So the code instructs the FPGA (or, more accurately, the Verilog compiler) to examine the number and set dispoutput based on the input. The <= character, by the way, are a non-blocking assignment.

This paper focuses on the implementation and simulation of 4-bit, 8-bit and 16-bit carry look-ahead adder based on Verilog code and compared for their performance in Xilinx.