News

IEEE20d
An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits
Abstract: This paper describes a 14nm test chip employing a novel NAND/NOR readout chain for characterizing soft error rate (SER) in combinational logic gates. The ...
IEEE24d
Memory and Logic soft error improvement using phase transition material assisted transistors
Abstract: Phase transition Material (PTM) assisted logic and SRAM bitcells have been proposed with improved soft error tolerance. The large insulating resistance of ...