Okay, now we’re beginning to feel a bit like [Alice]. This tutorial shows you how to simulate VHDL code. This code is intended to run on an FPGA and includes a software-only version of the AVR 8 ...

Encoder and decoder IP support the LDPC coding schemes as defined by the CCSDS 231.0-B-3 or the 142.0-B-1 versions of the standard. The IP Cores are available for ASIC and FPGA (Xilinx and Intel) ...

Currently, the code isn’t pipelined and a future task is to add pipelining so that it computes a new pixel on each clock cycle, after some latency, of course. The repo contains the VHDL code and ...