This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not ...

Due to the escalating need for compact and portable electronics, component shrinking is steadily advancing. Each logical procedure and component tend to lose energy as heat while being used.

The SG fault may not be detected by input vector 7 (CBA = 111) because BI/OUT1 is 0.53 V. Noise on this output could increase it and cause the inverter output (AI) to switch from a logic 1 to a logic ...