A Verilog-generation DSL for Julia. Inspired by Chisel, but we like Julia better. Not having to type in semicolons alone makes it worth it! Write your favorite verilog module as a julia function, by ...

stimc is a lightweight Verilog-VPI wrapper to simplify simulation control via C/C++ code similar to SystemC.In contrast to SystemC you can only use stimc together with a Verilog simulator and it is ...