One thing not detailed in the block diagram is whether Intel will enable AVX-512 on its mainstream Alder Lake Xeon processors. This is a feature that is disabled on Intel's consumer Alder Lake ...

Another block diagram of a more official nature leaked ... Chipset Engineering Interlock " dated May 2019 Ryzen 3000 as CPU (codenamed Matisse) will have a total of 24 PCIe Gen4 lanes.