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This project demonstrates the process of designing a circuit layout using a standard cell-based ASIC design flow. The aim was to implement the ASIC flow, starting from RTL design and simulation, ...
A structured application-specific integrated circuit (ASIC) has prefabricated yet configurable logic block arrays. We investigate some important via-configurable logic block (VCLB) design issues. We ...
In this paper, we describe a design of a mixed-signal circuit for an binary neuron (a.k.a perceptron, threshold logic gate) and a methodology for automatically embedding such cells in ASICs. The ...
BANGALORE, India — Engineers at Texas Instruments India have developed a new specification method for driving cell design flow, overcoming the current lack of a set process for specification capture ...
The project involves the full ASIC implementation steps from RTL to GDSII, where a standard cell of inverter was embedded inside a RISC-V architecture of picorv32a core and then the whole automated ...
From a design-tool perspective, the standard-cell approach offered the design team maximum flexibility. The design team could use a wide range of tools, from multiple vendors, to develop its ASIC.
FPGAs in the verification flow. Firstly let’s assume that a designer needs to create a structured ASIC or standard cell ASIC in order to meet one or more of the following design considerations: unit ...
ANAHEIM, Calif. — Cyclos Semiconductor Inc. announced a proof-of-concept processor implementation using its platform and standard-cell design flow. Cylcos said at the Design Automation Conference here ...
Figure 1 shows the typical block diagram of a Structured ASIC. Structured ASICs can include embedded CPUs and DSPs, blocks of embedded memory, analog circuitry and PLLs. Other blocks can exist ...