The problem for Infrant Technologies, a young network storage IC company, was to figure out how to avoid the typical iterative design scenario. For our latest design, a 250-MHz network storage device ...

When all is said and done, the structured ASIC’s shorter development cycle may well be the deciding factor for your design team. With the emergence of 90-nm process technology, ASIC designers ...

Physical Compiler proved to be effective in eliminating the design iterations often encountered in an ASIC flow due to the discrepancy between the gate load assumed by the wire-load model and that ...

SAN JOSE, CA --(Marketwired - July 19, 2016) - BaySand, the leader in application configurable ASICs, announces Xpresso, an online ASIC Wizard that facilitates the generation of IP blocks for ASIC ...

The change to physical synthesis, aka SP&R, aka RTL-to-GDS-II, design tools for the 0.13-micron and 90nm process nodes is pulling several other methods and tools previously reserved for the highest ...

Avnet ASIC Israel Ltd. (AAI) Standardizes on Synopsys' Design Compiler Graphical to Accelerate SoC Design Cycle. ... AAI uses advanced low power and design-for-test techniques within this flow.

According to Gartner Inc., the semiconductor industry achieved record revenue in 2005, and consumer ASICs (14% growth) and wireless ASICs (9% growth) played a significant role ...

So we adopted an ASIC design flow that was based on Magma's integrated RTL-to-GDSII system. We would use Blast Create to synthesize the design and then hand off the netlist to our ASIC vendor to ...