Design provided for an 8 bit Vedic Multiplier circuit using the Vedic Mathematics (Urdhva Tiryagbhyam sutra) for generating the partial products. The partial product addition in Vedic multiplier is ...

In this paper we have analyzed an 8-bit multiplier circuit using non clocked pass gate families with help of carry save multiplier (CSA) technique. The multiplier cell of the adder is designed by ...