So, here in this paper the Vedic multiplier circuit is implemented by using GDI technique and also 18nm FinFET is deployed for analyzing simulation results. Here, the primary objective is to optimize ...

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The proposed ΔΣ ADC is fabricated in a 65-nm LP CMOS process, and the active area is 0.38 mm 2. The fabricated ADC operates at supply voltages from 0.4 to 1 V. Depending on the supply voltage and ...