The objective of this mini-project was to design, implement, simulate, and verify a 4-bit Arithmetic Logic Unit (ALU) using Verilog HDL (Hardware Description Language). An ALU is a fundamental ...

Write your design in Verilog (or VHDL) and save it in a .v file. Synthesis: Use a synthesis tool to convert the Verilog code into a gate-level netlist. This netlist contains the logical representation ...