There is an exception to this. During simulation, Verilog does act like a programming language, but it has very specific rules for keeping the timing the same as it will be on the FPGA.

Testbench program block. In Verilog the testbench for a design must be modeled using Verilog hardware modeling constructs. Since these constructs were primarily intended for model hardware behavior at ...

You write Verilog and the tools create a bitstream ... Different FPGAs use different technology bases and that may affect how you program them. But it all starts with a bitstream (just a fancy ...

It also promises better simulation control and improved tool interoperability through an enhanced programming language interface (PLI). While chip designers have yet to get up to speed on Verilog-2001 ...

In both the hello.v and counter1.v examples, the compiler is given a source file that it compiles to a vvp-format output file, and the vvp program executes the generated file. In Verilog programs, ...

It’s a bit of a hybrid—the language combines HDLs and a hardware verification language using extensions to Verilog, plus it takes an object-oriented programming approach. SystemVerilog ...

It should be noted, however, that Z01X! is not fully IEEE compliant because it doesn't support the Verilog programming language interface (PLI). "We are not great believers in the PLI," said Williams.