You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench ... It may not be obvious, but ...

The difference is simple: combinatorial logic is all logic gates ... Verilog provides an initial block that is usually not valid for synthesis, but will be the main part of most test benches.

It is clear that the dump-all paradigm that is applicable to RTL logic is not meaningful for test-bench code for these reasons ... messages within the same environment as the design RTL or gate-level ...