The 10 bit value (output of the encoder, input to the decoder) have a reverse bit-order compared to the original verilog source The part in dec_8b10b.vhd that calculates code_err was rewritten ...

We construct a dataset for evaluating LLMs on VHDL code generation task. This dataset is constructed by translating a collection of Verilog evaluation problems to VHDL and aggregating publicly ...