Those verification suites usually involve large simulation test benches with complex infrastructures to support ... These were usually simple languages and each tool had it's own unique syntax and ...

Once TestBencher generates VHDL and Verilog test benches, they can be optionally linked to C++ code via the TestBuilder C++ library. TestBuilder also supplies an easier method for integrating C ...

Most traditional test benches already have this infrastructure in place (usually done with tasks in Verilog test benches) to deal with the manipulation and transfer of these packets.