Typically, since their inception, they have been x86 architecture-based, whereas nearly the entire world's smartphones are ...

RISC-V, pronounced “risk five,” is a modern open-source instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. In simple terms, it’s like a blueprint ...

With the continued integration of system functions onto a single chip and the push for more specialized functions like machine learning, the competition between processor architectures is heating ...

From the Institute of Computing Technology division of the Chinese Academy of Sciences and Peng Cheng Laboratory comes a high-performance and well-documented RISC-V core called XiangShan. In the Gi… ...

Called the Freedom E301 or FE310, alongside the RISC-V core are a whole bunch of peripherals (see diagram). The core runs at 320MHz, so this is a powerful beas, and it supports the following RISC-V ...

The Ethereum co-founder argued that implementing the RISC-V architecture in smart contracts would keep block production markets competitive and improve the efficiency of zero knowledge functions ...

The biggest news recently is that Google wants to make RISC-V a tier-one architecture for Android. 2D Android apps are written in Java and compiled for your processor (sometimes in the cloud!), so ...

Google wants RISC-V to be a “tier-1” Android architecture Google's keynote at the RISC-V Summit promises official, polished support.