In general, you want to avoid non-synthesizable Verilog except when writing your testbench (the driver for your simulation; I’ll talk more about it in a minute). Look back at the adder schematic.

A testbench, as it’s known in VHDL, or a test fixture in Verilog, is a construct that exists in a simulation environment such as ISim, ModelSim or NCsim. Simulation enables a unit under test (UUT) ...

Low power testbenches ... System Verilog APIs to can be used to query the UPF data model and monitor and control the UPF objects during simulation. This article explores different applications of the ...