#1 – New built-in data types Verilog provides reg and integer data types with 4 logic values for each bit. These multi-value data types are not always required for RTL-level modelling, where most ...

You use type std_logic for single-bit data types, which can have one of nine possible values: U, X, 0, 1, Z, W, L, H, or -. The IEEE library package STD_ Logic_1164 defines data type std_logic, along ...