This repository contains an implementation of Booth's Multiplier, a hardware algorithm widely used for multiplying binary numbers efficiently. The implementation supports 16-bit signed multiplication.

Design provided for an 8 bit Vedic Multiplier circuit using the Vedic Mathematics (Urdhva Tiryagbhyam sutra) for generating the partial products. The partial product addition in Vedic multiplier is ...

In this paper implementation of a high speed 16×16 bit booth multiplier based on novel 4-2 compressor structure has been discussed. Starting from the design of 4-2 compressor a new structure has been ...