This repository contains an implementation of Booth's Multiplier, a hardware algorithm widely used for multiplying binary numbers efficiently. The implementation supports 16-bit signed multiplication.

Low power and area efficient 16-bit multiplier has been designed and implemented using the Dadda algorithm. Here, the prime building block having low power dissipation and area efficient optimized ...

This paper describes a 16 /spl times/ 16 bit single-cycle 2's complement multiplier with a reconfigurable PLA control block fabricated in 90-nm dual-V/sub t/ CMOS technology, operating at 1 GHz, 9 mW ...